Verilog file for a 2-input AND

Verilog is a hardware description language that can be used to describe digital circuits. In this post we will show you how to describe a 2-input AND in a style that is supported by inPlace Pitanga virtual board. The description is given below and lines are numbered for easy referral.

1 module my_and2 (

2 input i1,

3 input i0,

4 output out);


6 // logic

7 and(out, i1, i0);

8 endmodule

The first line defines a module called my_and2. The name my_and2 is used to avoid conflict with reserved keywords in verilog. The second and third lines define two inputs called i1 and i0, respectively. The fourth line defines an output called out. The fifth line is an empty line and the sixth line is a comment indicating that the logic will be described next. the line number 7 describes the logic as an instantiation of a primitive 2-input and in verilog. Notice that the name of the signals come between parenthesis, separated by commas and the first signal listed is the output. The eight line ends the module and the verilog description. As you will see, this verilog description can be compiled directly into the inPlace Pitanga virtual board.

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