A structured project allows the development of complex systems from simpler subsystems. By using the concept of hierarchy, it is possible to compose circuits with a multitude of simpler subcircuits, making the whole system much more complex. In this tutorial, we will structure the "Hello World" project using Verilog module hierarchy.
In this tutorial, you will learn how to:
Redesign the "Hello World" circuit using subsystems (or modules)
Create Verilog modules for each of the circuits that print the letters 'O', 'L', and 'A' on the Community board display
Structure a hierarchical project using Verilog constructs
Map the circuit ports to the Community board display
Compile and prototype a hierarchical project on the Community board
Read and understand the project's summary report
Interact with a hierarchical project on the Community board
Click on the link below to download the code for this tutorial:
Before proceeding, we recommend the following tutorials.
Redesigning the "Hello World" circuit
The "Hello World" circuit has a single Verilog file containing the entire circuit description. To redesign it in a structured way, we need to decide which parts of the circuit will be transformed into modules (or subsystems). In this tutorial, we will modularize the circuits related to each letter, starting with modularizing the sub-circuit that activates/deactivates the segments that make up the letter 'L'. To do this, we will replace the 3 buffers indicated in the figure below with a module called 'letter_l'.
In the figure above, the three output signals of the buffers have been replaced by a 3-bit wide bus. This change was made to simplify the schematic and is commonly found in digital circuit design. Tables are also widely used in digital circuits. Through them, we describe the interface of modules. As an example of this, the description of the 'letra_l' module interface is provided below:
Gate | Direction | Bits | Description |
active | input | 1 | Activate the 3 segments required to display the letter 'L' on the display. |
dp_seg[2:0] | output | 3 | Signals that make up the letter 'L' on a seven-segment display. |
​ | ​ | ​ | ​ |
Describing modules in Verilog
With the design of the 'letra_l' module completed, we can now proceed with its implementation in Verilog code. Below is the description of the module:
module letra_l(
// Sinal de entrada conectado a chave
// que ativa a letra 'L'
input ativa,
// Sinais de saida conectados ao display
// de sete segmentos que compoem a letra 'L'
output [2:0] dp_seg
);
// Circuito que ativa os
// segmentos que compoem a letra 'L'
buf(dp_seg[2],ativa);
buf(dp_seg[1],ativa);
buf(dp_seg[0],ativa);
endmoduleSave the code above in a file called letra_l.v. Following the same procedure, try to describe the 'letra_o' and 'letra_a' modules yourself, saving them in files 'letra_o.v' and 'letra_a.v', respectively. If you are unable to do so, the code for both modules is provided below:
letra_o.v
letra_a.v
Creating the module hierarchy
Now that each of the 'letra_o', 'letra_l', and 'letra_a' modules are described in Verilog, we need to create another file to instantiate them. This file is called ola_mundo.v and is the top file in the hierarchy. In other words, the top file is the one that instantiates all the other files, as indicated in the schematic below.
Modules in the top file can be instantiated using the following syntax:
nome_do_modulo nome_da_instancia(
.porta_do_modulo(sinal_mapeado),
.porta_do_modulo(sinal_mapeado),
...
.porta_do_modulo(sinal_mapeado)
);Applying the syntax in the schematic above, we get the following code for the ola_mundo.v file:
module ola_mundo(
// Sinais de entrada conectados as chaves
// sw2, sw1 e sw0 da placa Pitanga
input chave_o,
input chave_l,
input chave_a,
// Sinais de saida conectados aos displays
// de sete segmentos da placa Pitanga
output [5:0] O,
output [2:0] L,
output [5:0] A
);
// Circuito que liga e desliga os
// segmentos que compoem a letra 'O'
letra_o DISPLAY_O(
.ativa(chave_o),
.dp_seg(O)
);
// Circuito que liga e desliga os
// segmentos que compoem a letra 'L'
letra_l DISPLAY_L(
.ativa(chave_l),
.dp_seg(L)
);
// Circuito que liga e desliga os
// segmentos que compoem a letra 'A'
letra_a DISPLAY_A(
.ativa(chave_a),
.dp_seg(A)
);
endmoduleMapping the ports on the Community board
The hierarchical circuit is ready, but the pin mapping file (.pinout) is still missing in order to prototype it on the Community board. This step follows the same steps as the previous tutorial. However, we have included the ola_mundo.pinout file below for your convenience.
// Porta Verilog Componentes da Placa
// Mapeia portas de entrada para as chaves
chave_a = sw0;
chave_l = sw1;
chave_o = sw2;
// Mapeia portas de saida correspondendo as
// letras 'O', 'L' e 'A' para o display de sete
// segmentos
O[5] = segd3.f_on;
O[4] = segd3.e_on;
O[3] = segd3.d_on;
O[2] = segd3.c_on;
O[1] = segd3.b_on;
O[0] = segd3.a_on;
L[2] = segd2.f_on;
L[1] = segd2.e_on;
L[0] = segd2.d_on;
A[5] = segd1.g_on;
A[4] = segd1.f_on;
A[3] = segd1.e_on;
A[2] = segd1.c_on;
A[1] = segd1.b_on;
A[0] = segd1.a_on;
Note that the mapping file is exactly the same as the one used in the previous tutorial.
Compiling the project
The compilation process translates the ola_mundo.v and ola_mundo.pinout files into the available logic cells on the Pitanga chip. It is through compilation that the digital circuit is built. To perform the compilation, follow the instructions below:
1) Open the Community board
. pitanga.sh
python pitanga.pyWindows Users can open the Community board by double-clicking the Pitanga link
2) Click on the 'Upload Files' button and select the ola_mundo.v, letra_o.v, letra_l.v, letra_a.v, and ola_mundo.pinout files. Then, click 'Run'.
If you have not made any coding errors in Verilog, the text terminal will print a report with a summary of the project. Note that the report contains the same number of buffers used in the previous project.
DESIGN SUMMARY REPORT
module : ola_mundo
design file: ola_mundo.v
pinout file: ola_mundo.pinout
Total number of wires: 0
Total number of cells: 15
Cell Instances Cell Instances Cell Instances
-----------------------------------------------------------------------------
AND2 0 | NAND2 0 | XOR2 0
AND3 0 | NAND3 0 | XOR3 0
AND4 0 | NAND4 0 | XOR4 0
OR2 0 | NOR2 0 | XNOR2 0
OR3 0 | NOR3 0 | XNOR3 0
OR4 0 | NOR4 0 | XNOR4 0
-----------------------------------------------------------------------------
BUF 15 | INV 0 | DFFRSE 0
Cells utilization: 15/500 cells (3.0 %).
3) Finally, click on the switches sw2, sw1, sw0 and check if the word 'OLA' appears on the seven-segment display. The expected result is shown in the following figure.
Conclusion
Congratulations! You have just prototyped a digital circuit without using FPGAs. With the help of the virtual Community board and the programmable Pitanga chip, you gained the experience of structuring a digital circuit in Verilog without spending a penny on buying protoboards or FPGA-based boards. Note that this same Verilog project can be prototyped on an FPGA-based board, working in the same way, provided that the mapping is done correctly for the seven-segment display.
Did you know that the Student board has a faster and larger Pitanga chip than the Community board? And that the Student board has no user limitations? So consider subscribing to one of our plans. Get in touch with us!
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