Your home network is connected to the internet through a fiber optic cable. It's just one cable, and all the devices in your home (phones, computers, tablets) are connected to this cable through a router. How is it possible for so many devices to use the same cable? The answer lies in the serialization and deserialization of data. The animation below demonstrates this concept through the transmission of an 8-bit word from a computer in your home (Device A) to a remote computer (Device B).
The transmission through device A is performed by the reg_tx register, which serializes the 8-bit word in reg_a. Similarly, device B deserializes the data received through the 1-bit channel using the reg_rx register and transfers it to the reg_b register. Despite having distinct purposes, both serializer and deserializer circuits use a similar circuit that shifts bits as they are captured. This circuit is known as a shift register (or "registrador de deslocamento" in Portuguese).
In this tutorial, you will learn how to:
instantiate and use the DFFRSE flip-flop of the virtual chip Pitanga
design an 8-bit register using the DFFRSE flip-flop
implement the project of a 10-bit shift register
map, compile, and prototype the project on the Community board
interact with the project on the Community board
Before proceeding, we recommend the following tutorials:
What is a flip-flop?
A flip-flop is a 1-bit storage device used in the design of sequential circuits. There are various types of flip-flops, each with distinct characteristics, with the most common being the D-type flip-flop. In the D-type flip-flop, the input is stored on the transitions of the system clock (or clock edges).
The Pitanga virtual chip has in its component library a D-type flip-flop, with write control, called DFFRSE. This flip-flop is described in the table below, where X indicates '0' or '1' (don't care). Note that the pins of DFFRSE have priorities if activated at the same time.
reset | set | enable | d | clk | q | Descrição |
1 | X | X | X | X | 0 | Reset assíncrono |
0 | 1 | X | X | X | 1 | Set assíncrono |
0 | 0 | 0 | X | X | q | Flip-flop desabilitado. Retém estado anterior. |
0 | 0 | 1 | 0 | ↑ | 0 | Flip-flop habilitado. Armazena entrada d na borda de subida do relógio. |
0 | 0 | 1 | 1 | ↑ | 1 | Flip-flop habilitado. Armazena entrada d na borda de subida do relógio. |
DFFRSE means D-type Flip-Flop with asynchronous Reset, Set and clock Enable
In the following sections, we will use this flip-flop to design an 8-bit shift register. To do this, it will be necessary to instantiate the DFFRSE using the following syntax:
DFFRSE nome_da_instancia(
.q(sinal_de_saida),
.d(sinal_de_entrada),
.clk(clock_do_sistema),
.reset(reset_do_sistema),
.set(set_do_sistema),
.enable(sinal_de_controle));Designing an 8-bits register
A register is a set of D-type flip-flops controlled by the same clock, reset/set, and enable signals. Registers store and transfer data in the form of bit vectors in synchronization with the system clock (clock signal).
The figure below shows the schematic of an 8-bit register. This register stores the 8-bit vector din on every rising edge of clk when enabled (cen = '1'). Note that, except for the data signals din and dout, all flip-flops in the 8-bit register are controlled by the same clk, set/reset, and enable signals.
Note: To facilitate the understanding of the schematic, the wires connecting the set and reset inputs of the DFFRSE have been omitted from the figure.
Describing the above register in Verilog, we obtain the following code:
module reg8b(
input rst, // reset assincrono
input set, // set assincrono
input cen, // habilita relogio (clock enable)
input clk, // relogio do sistema (clock)
input[7:0] din, // entrada de dados (data in)
output clk_out,// saida do sinal de clock
output[7:0] dout); // saida de dados (data out)
// registrador de 8 bits
DFFRSE dff0(.q(dout[0]), .d(din[0]), .clk(clk),.reset(rst), .set(set), .enable(cen));
DFFRSE dff1(.q(dout[1]), .d(din[1]), .clk(clk), .reset(rst), .set(set), .enable(cen));
DFFRSE dff2(.q(dout[2]), .d(din[2]), .clk(clk), .reset(rst), .set(set), .enable(cen));
DFFRSE dff3(.q(dout[3]), .d(din[3]), .clk(clk), .reset(rst), .set(set), .enable(cen));
DFFRSE dff4(.q(dout[4]), .d(din[4]), .clk(clk), .reset(rst), .set(set), .enable(cen));
DFFRSE dff5(.q(dout[5]), .d(din[5]), .clk(clk), .reset(rst), .set(set), .enable(cen));
DFFRSE dff6(.q(dout[6]), .d(din[6]), .clk(clk), .reset(rst), .set(set), .enable(cen));
DFFRSE dff7(.q(dout[7]), .d(din[7]), .clk(clk), .reset(rst), .set(set), .enable(cen));
// relogio do sistema (clock)
buf(clk_out, clk);
endmoduleSave the above file as reg8b.v, along with its pinout file reg8b.pinout.
reg8b.pinout
Next, open the Community virtual board, compile and prototype the register on the virtual Pitanga chip. The project summary report should be the same as shown below:
DESIGN SUMMARY REPORT
module : reg8b
design file: reg8b.v
pinout file: reg8b.pinout
Total number of wires: 0
Total number of cells: 9
Cell Instances Cell Instances Cell Instances
-----------------------------------------------------------------------------
AND2 0 | NAND2 0 | XOR2 0
AND3 0 | NAND3 0 | XOR3 0
AND4 0 | NAND4 0 | XOR4 0
OR2 0 | NOR2 0 | XNOR2 0
OR3 0 | NOR3 0 | XNOR3 0
OR4 0 | NOR4 0 | XNOR4 0
-----------------------------------------------------------------------------
BUF 1 | INV 0 | DFFRSE 8
Cells utilization: 9/500 cells (1.7999999999999998 %).Finally, considering that:
the reset signal is on button 0 (btn0);
the set signal is on button 1 (btn1);
the signal that enables the clock (cen) is on switch 9 (sw9);
the imput data is on the keys from 0 to 7 (sw0 .. sw7);
the output data of register is in the LED keys from 0 to 7 (led0 .. led7);
the clock signal is mapped to the flashing LED on LED9.
perform the following experiments in the project and notice that:
the rst signal has priority over the clock (asynchronous reset)
the set signal has priority over the clock (asynchronous set)
the register captures input data when enabled (cen = '1') only on transitions of LED9 from off to on.
The video below shows the behavior of the 8-bit register on the Community board.
Designing a shift register
Understanding the operation of the 8-bit register, let's move on to the objective of this article: designing a 10-bit shift register. In the circuit schematic below, the output of each flip-flop is connected to the input of the subsequent flip-flop. Thus, the input signal sdi (serial data in) propagates on each rising edge of the clock until it reaches the output port sdo (serial data out).
Set aside some time and try to code this project on your own. If you have difficulties, the code is just below.
Overall, it takes 10 clock cycles for the input signal sdi to reach the sdo output. Below, there is Verilog code and pinout.
shift8b.v
shift8b.pinout
Mapping, compiling, and prototyping
To prototype the shift register on the Community board, follow the steps below:
1) With the shift8b.v and shift8b.pinout files saved on your computer, open the Community board:
. pitanga.sh
python pitanga.pyWindows users can open the Community board by double-clicking on the Pitanga link.
2) Click on the "Upload Files" button and select the shift8b.v and shift8b.pinout files. Then, click on "Run".
If you have not made any coding errors in Verilog, a report with a summary of the project will be printed on the text terminal.
Summary report of the project
Done! You have just compiled and prototyped a 10-bit shift register on the programmable virtual chip Pitanga.
Interacting with the project on the Community board
With the project configured on the Community board, and considering that
The reset signal is on button 0 (btn0);
The set signal is on button 1 (btn1);
The serial input data is on button 2 (btn2);
The signal that enables the clock (clock enable, cen) is on switch 9 (sw9);
The output data from the register is on LEDs 0 to 9 (led0 .. led9);
try to play around with the circuit a bit. Notice that it works exactly like the reg_rx register presented in the animation at the beginning of this article. The only difference is in the size of the shift register, which in this project has 10 bits.
Below, the same project running on two different virtual boards.
Sign up for the Pitanga Student Edition and see the shift register operating at higher clock frequencies.
Placa Community (1 Hz) | Placa Student (5 Hz) |
Conclusion
Congratulations! You have just prototyped a digital circuit without using FPGAs. With the help of the Community virtual board, you gained the experience of designing registers using the flip-flops of the virtual programmable Pitanga chip. You were also able to design and prototype a shift register, understanding the importance of this circuit for telecommunications.
Did you know that the Student board has a faster and larger Pitanga chip with more logic cells than the Community board? And that the Student board has no user limitation? So, consider subscribing to one of our plans. Get in touch with us!
Comments