We have enhanced the Pitanga toolchain by incorporating a new compiler and bringing substantial improvements over the previous toolchain. As indicated in the figure below, Pitanga 23.12 (Armada) includes:

1. The slang compiler, used for syntax analysis of Verilog files;

2. The yosys/abc synthesizer, used for mapping the circuit to the logic cells available in the Pitanga virtual library; and

3. Our Pitanga emulator, used for emulation, providing you with the experience of designing digital circuits easily, quickly, and in real time.

   
   

With Pitanga 23.12, it's now easier to identify various syntax errors that were not as clear in previous versions. Additionally, the new version of Pitanga stands out for its more detailed error reporting, making it simpler to investigate and understand issues in project files.