In this latest update, we've integrated the open-source Yosys synthesizer with the Pitanga virtual cell library. As a result, users can now design more robust and complex circuits in Verilog, which are then mapped to the cells of the Pitanga programmable virtual chip.

The Pitanga virtual cell library includes buffers (BUF), inverters (INV), flip-flops (DFFRSE), as well as:

• AND2, OR2, NAND2, NOR2, XOR2, XNOR2

• AND3, OR3, NAND3, NOR3, XOR3, XNOR3

• AND4, OR4, NAND4, NOR4, XOR4, XNOR4

  
  

By combining Yosys with Pitanga, InPlace significantly enhances the quality of its digital circuit design platform.

About Yosys

Yosys is an open-source logic synthesis framework for FPGAs (Field Programmable Gate Arrays) and integrated circuits. It functions as a logic synthesis tool, converting high-level hardware descriptions written in languages like Verilog into an optimized netlist representation for implementation in FPGAs or ASICs (Application-Specific Integrated Circuits).